A serial interface is often used in integrated circuits to establish communication with a host system over a serial bus. Typically, communication over the serial bus is standardized by a serial message protocol, such as e.g. the Inter-Integrated Circuit I2C protocol. Inside the integrated circuit, the serial message protocol is often decoded into some form of internal read or write access on an internal bus that are caused by a received message. An internal read access must complete before the first bit of data is expected to appear on the serial interface according to the serial message protocol used. Depending on which register or device is concerned by the read access, the read access may take a different number of clock cycles to complete. For example, a slow memory or slow IO port may cause a violation of timing constraints of the serial message protocol. Moreover, the read access may even be forwarded by the integrated circuit to a device which is external to the integrated circuit and connected with the latter via a bridge. In this case, a violation of the timing constraints is almost unavoidable and an efficient mechanism is needed to avoid degradation of the system performance.
If it isn't possible to meet the timing constraints of the serial message protocol, the data transfer on the external serial bus must be extended using some form of wait state mechanism. Alternatively, the clock cycle of the host system may be stretched or a negative acknowledgement NACK signal must be returned form the integrated circuit to the host system, indicating that the access attempt has failed. In any case, the whole system is slowed down and the overall performance deteriorated.